In recent years, it has been progressed in the process of a semiconductor device having a CMOS logic circuit for making the device with a fine construction by utilizing a scaling law. In such a process, it is general to use a method for forming a metal silicate layer of a refractory metal in a source/drain region of a MOS transistor by using a salicide technology for the purpose of reducing the parasitic resistance. The salicide technology is a process for forming a metal silicide layer of a refractory metal selectively and self-adjustingly on a surface of a silicon gate electrode and a source/drain region of a MOS transistor at the same time. Additionally, with respect to a semiconductor device having a CMOS logic circuit, total system unification on a silicon substrate has been highly demanded for the purpose of a fine construction of a device and at the same time for the purpose of reduction of power consumption, improvement of operation speed and lower cost. For example, it has become an important theme how to form a functional device such as a CMOS image sensor and a logic LSI with embedded DRAM.
However, it is technically difficult to unify a CMOS logic region where a metal silicide layer of a refractory metal is formed in a source region and a drain region with a solid-state imaging device having DRAM cells and photodiodes where there is a problem of a junction leak current on a single silicon substrate. In more detail, when metal silicide layers of a refractory metal are formed in a source region and a drain region, it causes an increase of a junction leak current and it especially becomes a fatal problem for a solid-state imaging device having DRAM cells and photodiodes where a junction leak current is a matter of a problem. The metal silicide layers of a refractory metal are formed by forming a metal of a refractory metal on the surfaces of the source region and the drain region and by reacting the silicon and the metal of a refractory metal. However, when the silicon and the metal of a refractory metal do not completely react each other and the metal of a refractory metal which does not react owing to some probability remains in the vicinity of a junction, it causes an increase of a junction leak current in response to a fact that the remaining metal of a refractory metal becomes a core.
On the other hand, it is adopted for a MOS transistor that a source region and a drain region are made as an LDD structure by utilizing an insulating film spacer formed at the gate electrode and the side wall thereof, that is, a so-called sidewall. Then, by using, for example, a photo-resist method, a method is proposed where an etchingback process is applied only to a CMOS logic region where metal silicide layers of a refractory metal are formed such that the metal silicide layers of a refractory metal are formed only in the source region and the drain region in the CMOS logic region. However, in case of this method, there is a problem that either of the source region and the drain region cannot be formed in a region where the metal silicide layer of a refractory metal is not formed.
Consequently, in case of forming a source region and a drain region having a relatively deep junction, a sidewall structure becomes necessary in order to avoid an influence towards the channel region of the MOS transistor. As mentioned above, when the same region is used for a region formed with a metal silicide layer of a refractory metal and a region formed with a sidewall, a sidewall cannot be formed in a region where the metal silicide layer of a refractory metal in not formed and it becomes impossible to form the source region and the drain region in a forming region and in a non-forming region of a metal silicide layer of a refractory metal at the same time. In a CMOS image sensor, for example, a picture quality has been attempted to improve by making the potential setting of the photodiode deeper such that the saturation signal is increased and the S/N ratio is made larger. However, in response to setting the potential of the photodiode deeper, the potential setting of the source/drain regions of the MOS transistor for reading-out should be made deeper in order to read out the signal charge of the photodiode. As to this means, it becomes indispensable to form a source/drain region by injecting an impurity of a high concentration using the sidewall as a mask. In other words, it is necessary to form source/drain regions also in an area of picture elements where a metal silicide layer of a refractory metal is not formed, but there has been a theme in the prior art technique that such a necessity cannot be cleared.
It should be noted that a JAP laid-open patent No. 2001-44404 discloses about a constitution of forming a metal silicide layer in a source/drain region of a MOS transistor connected to a light receiving portion.